1. Field of the Invention
The present invention relates to a transistor structure and its fabricating method thereof, and particularly, to a transistor structure which is constructed for a LOW voltage operation.
2. Discussion of Related Art
FIG. 1 is a layout of a conventional unit transistor and FIG. 2 is a cross sectional view taken in the direction of the arrows along the line II--II of FIG. 1. Further, FIG. 3 is a circuit diagram of a prior art SRAM cell and FIG. 4 is a cross sectional view, having the same perspective as FIG. 2, showing the structure of the access and drive transistors of a conventional SRAM cell. In addition, FIGS. 5a-5d are diagrams illustrating the method of fabricating the access and drive transistors of the conventional SRAM cell.
A conventional unit transistor, as shown in FIGS. 1 and 2, include a substrate 1 which defines a field region and an active region, a field oxide layer 2 formed on the surface of the field region of the substrate 1, a gate oxide layer 3 and a gate electrode 4 laminated on the active region, and first and second impurity regions 5a and 5b serving as the source and drain of the transistor disposed in a predetermined region of the substrate on each side of the gate electrode 4. Accordingly in FIG. 2, the impurity diffused regions 5a and 5b would extend out from the page and extend into the page.
A prior art access and drive transistor structure of a prior art SRAM, as shown in FIG. 4, includes a substrate 1 which defines an active region 5, a field region and a field oxide layer 9 formed thereon, a gate oxide layer 11 formed on a respective active region which are separated by a field oxide layer 9, and a gate electrode 12a of the access transistor and a gate electrode 12b of the drive transistor which are laminated on the gate oxide layers 11.
Referring to FIG. 5a, a first pad oxide layer 6 and a nitride layer 7 are sequentially deposited on the whole surface of the substrate 1. Then, a first photoresist 8 is deposited on the whole surface of the nitride layer 7 and selectively patterned by a photoetching and development method.
In FIG. 5b, the patterned photoresist 8 is used as a mask for performing anisotropic etching on the exposed nitride layer 7 and then the photoresist 8 is removed. Next, the field oxide layer 9 is deposited on the substrate 1 by a thermal oxidation method using the remaining nitride layer 7 as a mask, and the active region of the access transistor is separated from that of the drive transistor.
As shown in FIG. 5c, after the nitride layer 7 and the first pad oxide layer 6 are removed, a second pad oxide layer 10 is deposited by a thermal oxidation or a chemical vapor deposition method. The second pad oxide layer 10 is removed after performing an implantation of channel stop ions in the active regions of the access and drive transistors.
In FIG. 5d, an oxide layer is deposited by a heat oxidation or a chemical vapor deposition method. Then, a polysilicon layer is deposited on the oxide layer, which is doped with an impurity. A second photoresist is paved on the polysilicon layer and selectively patterned by means of an exposure and a development method. Then, the polysilicon layer and the oxide layer are sequentially removed by using the patterned second photoresist as a mask. A gate electrode 12a of an access transistor and a gate electrode 12b of a drive transistor are then laminated on the gate oxide layer 11 which is formed on the active region. Finally, the second photoresist is removed.
FIG. 3 is a circuit diagram of a prior art SRAM cell illustrating a write/read operation. The write operation includes writing a high voltage at the contact region C4 to achieve a "1" state (i.e., a HIGH node) and writing a low voltage at the contact region C5 to achieve a "0" state (i.e., a LOW node). The read operation determines whether the cell is a HIGH node or a LOW node by sensing a voltage difference on the bit line B/L and the bit bar line (B/L).
To write a HIGH voltage to a fourth contact region C4, V.sub.CC is applied to a bit line B/L and the gate of a first access transistor TA1 which is connected to a word line W/L. Because of the applied V.sub.CC, the first access transistor TA1 is turned on and the V.sub.CC of the bit line B/L is stored in the forth contact region C4.
To write a LOW voltage to a fifth contact region C5, `0 V` is applied to a bit bar line (B/L) and V.sub.CC voltage is applied to the gate of a second access transistor TA2 which is connected to the word line W/L. Because of the applied V.sub.CC, the second access transistor TA2 is turned on and the LOW voltage of 0 V of the bit bar line (B/L) is written to the fifth contact region C5.
To read the HIGH voltage written at the fourth contact region C4, V.sub.CC voltage is applied to the gates of the first and second access transistors TA1 and TA2 which are connected to the word line W/L. In the state the V.sub.CC voltage stored at the fourth contact region C4 transfers to the bit line B/L and the 0 V voltage stored at the fifth contact region C5 transfers to the bit bar line (B/L), V.sub.CC voltage is fixed on the bit line B/L and 0 V voltage is fixed on the bit bar line (B/L), and a sensing amplifier senses the difference between these two voltages so as to determine which is a HIGH node or a LOW node.
While the forth contact region C4 and the fifth contact region C5 store the HIGH voltage and the LOW voltage, respectively, a second drive transistor TD2 is turned on and a first drive transistor TD1 is turned off. Because the second access transistor TA2 is turned on due to the V.sub.CC voltage applied to the word line W/L and a LOW voltage of the fifth contact region C5, the LOW voltage of the fifth contact region C5 passes from the bit bar line (B/L) through the second access transistor TA2 and the second drive transistor TD2 which is on due to the high voltage stored at the fourth contact region C4.
The LOW voltage of the fifth contact region C5 is determined by the resistance ratio of the second access transistor TA2 to the second drive transistor TD2 in the process. Therefore, to maintain the initial LOW voltage of the fifth contact region C5, the driving capability of the second drive transistor TD2 has to be three times as large of that of the second access transistor TA2.
Consequently, to maintain the initial voltage of the fifth contact region C5 during a read operation of the LOW node, a reduced current driving capability for a second access transistor is required and an increased current driving capability for a second drive transistor is required. Considering the dimensions of the access and drive transistors, the threshold voltage of the second access transistor TA2 needs to be increased and that of the second drive transistor TD2 needs to be reduced.
Contrary to maintaining a LOW node, in order to maintain the initial HIGH voltage at the forth contact region C4 during a read operation of the HIGH node, it is necessary to decrease the threshold voltage of the first access transistor TA1 and increase the threshold voltage of the first drive transistor TD1.
As described above, for a stable read operation, the threshold voltage of the access transistor at a LOW node is to be increased and that of the drive transistor is to be decreased so as to secure an operational margin of a stable low-voltage SRAM cell. However, it is difficult to secure an operational margin for a low operation voltage using the conventional access transistor.
The problems presented by the conventional transistor may be summarized as follows.
First, it is difficult to fabricate access and drive transistors which have characteristics opposite to each other during a write and read operation of a single cell SRAM.
Second, fabrication methods that will lower the threshold voltage of the access transistor in a HIGH node and increase the threshold voltage in a LOW node are not applicable to conventional SRAM transistor channels forming a SRAM cell needed to operate with a low voltage power source.